Svein Anders Tunheim

• Tunheim, Svein Anders; Zheng, Yujin; Jiao, Lei; Shafik, Rishad; Yakovlev, Alex & Granmo, Ole-Christoffer (2025). An All-Digital 8.6-nJ/Frame 65-nm Tsetlin Machine Image Classification Accelerator. IEEE Transactions on Circuits and Systems I: Regular Papers. ISSN 1549-8328. 73(2), p. 1107–1120. doi: 10.1109/TCSI.2025.3586698. Full text in Research Archive Show summary

  We present an all-digital programmable machine learning accelerator chip for image classification, underpinning on the Tsetlin machine (TM) principles. The TM is an emerging machine learning algorithm founded on propositional logic, utilizing sub-pattern recognition expressions called clauses. The accelerator implements the coalesced TM version with convolution, and classifies booleanized images of 28×28 pixels with 10 categories. A configuration with 128 clauses is used in a highly parallel architecture. Fast clause evaluation is achieved by keeping all clause weights and Tsetlin automata (TA) action signals in registers. The chip is implemented in a 65 nm low-leakage CMOS technology, and occupies an active area of 2.7 mm2. At a clock frequency of 27.8 MHz, the accelerator achieves 60.3 k classifications per second, and consumes 8.6 nJ per classification. This demonstrates the energy-efficiency of the TM, which was the main motivation for developing this chip. The latency for classifying a single image is 25.4 μ s which includes system timing overhead. The accelerator achieves 97.42%, 84.54% and 82.55% test accuracies for the datasets MNIST, Fashion-MNIST and Kuzushiji-MNIST, respectively, matching the TM software models.

• Tunheim, Svein Anders; Lei, Jiao; Shafik, Rishad; Yakovlev, Alex & Granmo, Ole-Christoffer (2024). Tsetlin Machine-Based Image Classification FPGA Accelerator With On-Device Training. IEEE Transactions on Circuits and Systems I: Regular Papers. ISSN 1549-8328. 72(2), p. 830–843. doi: 10.1109/TCSI.2024.3519191. Full text in Research Archive
• Tunheim, Svein Anders; Lei, Jiao; Shafik, Rishad Ahmed; Yakovlev, Alexandre & Granmo, Ole-Christoffer (2023). Convolutional Tsetlin Machine-based Training and Inference Accelerator for 2-D Pattern Classification. Microprocessors and Microsystems: Embedded Hardware Design (MICPRO). ISSN 0141-9331. 103. doi: 10.1016/j.micpro.2023.104949. Full text in Research Archive Show summary

  The Tsetlin Machine (TM) is a machine learning algorithm based on an ensemble of Tsetlin Automata (TAs) that learns propositional logic expressions from Boolean input features. In this paper, the design and implementation of a Field Programmable Gate Array (FPGA) accelerator based on the Convolutional Tsetlin Machine (CTM) is presented. The accelerator performs classification of two pattern classes in 4 × 4 Boolean images with a 2 × 2 convolution window. Specifically, there are two separate TMs, one per class. Each TM comprises 40 propositional logic formulas, denoted as clauses, which are conjunctions of literals. Include/exclude actions from the TAs determine which literals are included in each clause. The accelerator supports full training, including random patch selection during convolution based on parallel reservoir sampling across all clauses. The design is implemented on a Xilinx Zynq XC7Z020 FPGA platform. With an operating clock speed of 40 MHz, the accelerator achieves a classification rate of 4.4 million images per second with an energy per classification of 0.6 J. The mean test accuracy is 99.9% when trained on the 2-dimensional Noisy XOR dataset with 40% noise in the training labels. To achieve this performance, which is on par with the original software implementation, Linear Feedback Shift Register (LFSR) random number generators of minimum 16 bits are required. The solution demonstrates the core principles of a CTM and can be scaled to operate on multi-class systems for larger images.

• Tunheim, Svein Anders; Lei, Jiao & Granmo, Ole-Christoffer (2023). Model Export for the Convolutional Coalesced Tsetlin Machine, 2023 International Symposium on the Tsetlin Machine (ISTM). IEEE (Institute of Electrical and Electronics Engineers). ISSN 9798350344776. doi: 10.1109/ISTM58889.2023.10455048. Full text in Research Archive
• Abeyrathna, Kuruge Darshana; Abouzeid, Ahmed Abdulrahem Othman; Bhattarai, Bimal; Giri, Charul; Glimsdal, Sondre & Granmo, Ole-Christoffer [Show all 11 contributors for this article] (2023). Building Concise Logical Patterns by Constraining Tsetlin Machine Clause Size. In Elkind, Edith (Eds.), Proceedings of the Thirty-Second International Joint Conference on Artificial Intelligence. AAAI Press. ISSN 9781956792034. p. 3395–3403. doi: 10.24963/ijcai.2023/378. Full text in Research Archive Show summary

  Tsetlin machine (TM) is a logic-based machine learning approach with the crucial advantages of being transparent and hardware-friendly. While TMs match or surpass deep learning accuracy for an increasing number of applications, large clause pools tend to produce clauses with many literals (long clauses). As such, they become less interpretable. Further, longer clauses increase the switching activity of the clause logic in hardware, consuming more power. This paper introduces a novel variant of TM learning – Clause Size Constrained TMs (CSC-TMs) – where one can set a soft constraint on the clause size. As soon as a clause includes more literals than the constraint allows, it starts expelling literals. Accordingly, oversized clauses only appear transiently. To evaluate CSC-TM, we conduct classifcation, clustering, and regression experiments on tabular data, natural language text, images, and board games. Our results show that CSC-TM maintains accuracy with up to 80 times fewer literals. Indeed, the accuracy increases with shorter clauses for TREC, IMDb, and BBC Sports. After the accuracy peaks, it drops gracefully as the clause size approaches a single literal. We fnally analyze CSC-TM power consumption and derive new convergence properties.

• Bhattarai, Bimal; Granmo, Ole-Christoffer; Lei, Jiao; Andersen, Per-Arne; Tunheim, Svein Anders & Shafik, Rishad Ahmed [Show all 7 contributors for this article] (2023). Contracting Tsetlin Machine with Absorbing Automata, 2023 International Symposium on the Tsetlin Machine (ISTM). IEEE (Institute of Electrical and Electronics Engineers). ISSN 9798350344776. doi: 10.1109/ISTM58889.2023.10455040. Full text in Research Archive
• Sahu, Prajwal Kumar; Boppu, Srinivas; Shafik, Rishad Ahmed; Tunheim, Svein Anders; Granmo, Ole-Christoffer & Cenkeramaddi, Linga Reddy (2023). Enhancing Inference Performance through Include only Literal Incorporation in Tsetlin Machine, 2023 International Symposium on the Tsetlin Machine (ISTM). IEEE (Institute of Electrical and Electronics Engineers). ISSN 9798350344776. doi: 10.1109/ISTM58889.2023.10455016. Full text in Research Archive
• Tunheim, Svein Anders; Yadav, Rohan Kumar; Lei, Jiao; Shafik, Rishad & Granmo, Ole-Christoffer (2022). Cyclostationary Random Number Sequences for the Tsetlin Machine. In Fournier-Viger, Philippe; Fujita, Hamido; Ali, Moonis & Wang, Yinglin (Ed.), Advances and Trends in Artificial Intelligence. Theory and Practices in Artificial Intelligence. 35th International Conference on Industrial, Engineering and Other Applications of Applied Intelligent Systems, IEA/AIE 2022, Kitakyushu, Japan, July 19–22, 2022, Proceedings. Springer. ISSN 9783031085291. p. 844–856. doi: 10.1007/978-3-031-08530-7_71. Full text in Research Archive Show summary

  The Tsetlin Machine (TM) constitutes an emerging machine learning algorithm that has shown competitive performance on several benchmarks. The underlying concept of the TM is propositional logic determined by a group of finite state machines that learns patterns. Thus, TM-based systems naturally lend themselves to low-power operation when implemented in hardware for micro-edge Internet-of-Things applications. An important aspect of the learning phase of TMs is stochasticity. For low-power integrated circuit implementations the random number generation must be carried out efficiently. In this paper, we explore the application of pre-generated cyclostationary random number sequences for TMs. Through experiments on two machine learning problems, i.e., Binary Iris and Noisy XOR, we demonstrate that the accuracy is on par with standard TM. We show that through exploratory simulations the required length of the sequences that meets the conflicting tradeoffs can be suitably identified. Furthermore, the TMs achieve robust performance against reduced resolution of the random numbers. Finally, we show that maximum-length sequences implemented by linear feedback shift registers are suitable for generating the required random numbers.

• Glimsdal, Sondre; Saha, Rupsa; Bhattarai, Bimal; Giri, Charul; Sharma, Jivitesh & Tunheim, Svein Anders [Show all 7 contributors for this article] (2022). Focused Negative Sampling for Increased Discriminative Power in Tsetlin Machines. In Shafik, Rishad (Eds.), 2022 International Symposium on the Tsetlin Machine (ISTM 2022). IEEE (Institute of Electrical and Electronics Engineers). ISSN 9781665471169. p. 73–80. doi: 10.1109/ISTM54910.2022.00021. Full text in Research Archive Show summary

  Tsetlin Machines learn from input data by creating patterns in propositional logical, using the literals available in the data. These patterns vote for the classes in a classification task. Despite their simplistic premise, Tsetlin machine (TM)s have been performing at with other popular machine learning methods across various benchmarks. Not only accuracy, TMs also perform well in terms of energy efficiency and learning speed. The general TM scheme works best when there is sufficient discriminatory information available between two classes. In this paper, we explore the use of focused negative sampling (FNS) to discriminate between classes which are not easily distinguishable from each other. We carry out experiments across diverse classification tasks ranging over natural language processing, image processing, reinforcement learning to show that this approach forces the TM to arrive at patterns that can successfully tell apart two classes that are correlated. Further, we show that the proposed method achieves accuracy comparable to a vanilla Tsetlin Machine approach but in approximately 42% less number of epochs on average

• Tunheim, Svein Anders; Lei, Jiao; Shafik, Rishad Ahmed; Yakovlev, Alexandre & Granmo, Ole-Christoffer (2022). A Convolutional Tsetlin Machine-based Field Programmable Gate Array Accelerator for Image Classification. In Shafik, Rishad (Eds.), 2022 International Symposium on the Tsetlin Machine (ISTM 2022). IEEE (Institute of Electrical and Electronics Engineers). ISSN 9781665471169. p. 21–28. doi: 10.1109/ISTM54910.2022.00013. Full text in Research Archive Show summary

  This paper presents a Field Programmable Gate Array (FPGA) implementation of an image classification accelerator based on the Convolutional Tsetlin Machine (CTM). The work is a concept design, and the solution demonstrates recognition of two classes in 4 × 4 images with a 2 × 2 convolution window. More specifically, there are two sub-Tsetlin Machines (TMs), one per class. A single sub-TM employs 40 clauses, each controlled by 20 Tsetlin Automata. The accelerator features random patch selection, in parallel for all clauses, based on reservoir sampling. The design is implemented in a Xilinx Zync XC7Z020 FPGA. With an operating clock speed of 30 MHz, the accelerator is capable of inferring at the rate of 3.3 million images per second with an additional power consumption of 20 mW from idle mode. The average test accuracy is 96.7% when trained on data with 10% noise. A training session with 100 epochs and 8192 examples takes 1.5 seconds. Due to the limited hardware resources required, the CTM accelerator represents a promising concept for online learning in energy-frugal systems. The solution can be scaled to multi-class systems and larger images.

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• Sahu, Prajwal Kumar; Boppu, Srinivas; Shafik, Rishad Ahmed; Tunheim, Svein Anders; Granmo, Ole-Christoffer & Cenkeramaddi, Linga Reddy (2023). Enhancing Inference Performance through Include only Literal Incorporation in Tsetlin Machine. Full text in Research Archive
• Tunheim, Svein Anders; Lei, Jiao & Granmo, Ole-Christoffer (2023). Model Export for the Convolutional Coalesced Tsetlin Machine. Full text in Research Archive
• Tunheim, Svein Anders (2025). Hardware Acceleration of Convolutional Tsetlin Machines for Image Classification. Universitetet i Agder. ISSN 9788284272870. Full text in Research Archive Show summary

  Edge AI enheter i kommunikasjonsnettverk utfører kunstig intelligens-oppgaver lokalt. De har vanligvis begrensede ressurser mht. prosessering og maskinvare, og må operere med lave energibudsjetter. Den logikkbaserte strukturen til Tsetlin maskin (TM)-algoritmen krever ikke komplekse aritmetiske kretser, som vanligvis er nødvendige for dype nevrale nettverk. TM er derfor egnet for kretsløsninger med lavt strømforbruk. Målet med denne avhandlingen var å utvikle lav-effekt maskinvareakseleratorer for bildeklassifisering i Edge AI enheter, basert på TM med bruk av konvolusjon. For å oppnå dette begynte vi forskningen med å finne krav til generatorer av tilfeldige tall, som er viktige moduler i TM. Deretter implementerte vi en akselerator basert på vanilje-TM med konvolusjon (CTM), for datasettet “2D noisy XOR” i en felt-programmerbar portmatrise (FPGA). Videre implementerte vi en coalesced TM med konvolusjon (ConvCoTM), for operasjon på datasettet MNIST, også denne i en FPGA. Til slutt designet vi en applikasjonsspesifikk integrert krets (ASIC) basert på ConvCoTM, og viste at en slik krets kan oppnå lavt effektforbruk. Høy grad av parallell prosessering ble benyttet for alle løsningene. De følgende avsnittene gir en kort beskrivelse av hvert design med tilhørende ytelse. Under TM trening er effektiv og pålitelig generering av tilfeldige tall avgjørende i forbindelse med tilfeldig oppdatering av logiske regler og Tsetlin-automater (TAer) samt tilfeldig valg av delbilder. Sykliske stasjonære følger av tilfeldige tall, med minst 65 k elementer, ble funnet å være tilstrekkelig for å opprettholde nøyaktigheten til TM for datasettene som ble testet. For å oppfylle dette kravet i maskinvare, implementerte vi modul-banker med parallelle, lineært-tilbakekoblede skift-registre, alle med forskjellige starttilstander, og med en lengde på minst 16 bit. Disse modulene genererte de nødvendige tallfølgene for bruk ved stokastiske valg under TM trening, uten at nøyaktighet eller ytelse ble redusert. For CTM ble en akselerator for mønstergjenkjenning, med bruk av datasettet “2D Noisy XOR”, implementert i en FPGA. Denne løsningen støttet både trening og inferens, og oppnådde en testnøyaktighet på 99,9% som var på samme nivå som programvareversjonen. Dette var den første rapporterte maskinvareløsningen basert på CTM. En FPGA-implementering av en ConvCoTM-akselerator med 128 logiske regler ble også utviklet. Løsningen støttet komplett trening, med minimale krav til interaksjon med hovedprosessoren i systemet. For det velkjente MNIST-datasettet, som består av håndskrevne tall, ble det oppnådd en testnøyaktighet på 97,6%. Med en klokkefrekvens på 50 MHz utførte akseleratorkjernen 134 k bildeklassifiseringer per sekund, og en enkelt treningsperiode med 60 k bildeeksempler tok 1,5 sekunder. Dette var den første rapporterte maskinvareløsningen basert på ConvCoTM. For å demonstrere ultra-lavt strømforbruk ble en ConvCoTM-basert ASIC designet. Dette var en synkron, fullstendig digital inferens-akselerator med 128 logiske regler. Kretsen ble implementert i en 65 nm CMOS-teknologi, og var den første ASICen basert på ConvCoTM. Akseleratoren oppnådde en testnøyaktighet for MNIST på 97,42%, som samsvarte eskakt med programvaremodellen. Ved en klokkefrekvens på 27,8 MHz oppnådde ASICen 60.3 k klassifiseringer per sekund. Energiforbruket per klassifisering ble målt til 8,6 nJ. Dette var det nest laveste resultatet for alle rapporterte løsninger av produserte brikker, som opererer på MNIST og har sammenlignbar testnøyaktighet, og det laveste resultatet for en helt digital løsning. For å oppnå høy prosesseringsrate i akseleratorene i inferens-modus, ble alle logiske regler prosessert i parallell per delbilde som ble generert under konvolusjonen. De forskjellige klasse-summer ble deretter beregnet parallelt, med påfølgende klasseprediksjon. Også for trening ble samme grad av parallell prosessering benyttet. Alle logiske regler ble evaluert i parallell per delbilde, og i tillegg ble det benyttet en reservoar-utvalgsmekanisme for tilfeldig valg av delbilde per logisk regel. Oppdatering av logiske regler ble utført en om gangen, med parallell oppdatering av alle tilhørende TA-er. Disse arkitekturvalgene utgjorde en god avveining mellom bruk av maskinvareressurser og ytelse. Maskinvarearkitekturene som ble utviklet for CTM og ConvCoTM, er godt egnet for skalering og bruk på større og mer komplekse bilder. Det ble identifisert tydelige avveininger mellom prosesseringsrate og bruk av maskinvareressurser. Med de FPGA-baserte akseleratorene ble det demonstrert mulighet for å utføre komplett TM trening, noe som muliggjør Edge AI enheter som kan lære kontinuerlig.

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