Alexandre Yakovlev

• Roland, Markus Heyerdahl; Aunet, Snorre & Yakovlev, Alexandre (2025). Faster Training of Tsetlin Machines With Deterministic Multi-Step Automata. In Lei, Jiao & Shafik, Rishad Ahmed (Ed.), Tsetlin Machine (ISTM), International Symposium on the. IEEE (Institute of Electrical and Electronics Engineers). ISSN 9798331569228. p. 48–55. doi: 10.1109/ISTM67926.2025.00016. Full text in Research Archive Show summary

  This article investigates the use of "multi-step variable structure finite-state" automata (MVFA) in place of Tsetlin automata (TA) for a software implementation of the coalesced Tsetlin machine (CoTM) with up to 2048 clauses for classification of the MNIST dataset. The use of deterministic MVFA compared to TA resulted in a harmonic mean speedup of 5.6 times for training time per epoch and a mean increase in accuracy of 0.23% over the last 10 out of 50 epochs of training for the model sizes investigated. For CoTM with 1024 clauses, it was here observed that TA requires a minimum of 7 bits of state to obtain maximal first epoch accuracy, while MVFA requires a minimum of 10–12 bits. In light of previous work on MVFA, the findings presented here points to that the optimal choice of stochastic vs. deterministic automata depends on characteristics of the dataset.

• Tunheim, Svein Anders; Lei, Jiao; Shafik, Rishad Ahmed; Yakovlev, Alexandre & Granmo, Ole-Christoffer (2023). Convolutional Tsetlin Machine-based Training and Inference Accelerator for 2-D Pattern Classification. Microprocessors and Microsystems: Embedded Hardware Design (MICPRO). ISSN 0141-9331. 103. doi: 10.1016/j.micpro.2023.104949. Full text in Research Archive Show summary

  The Tsetlin Machine (TM) is a machine learning algorithm based on an ensemble of Tsetlin Automata (TAs) that learns propositional logic expressions from Boolean input features. In this paper, the design and implementation of a Field Programmable Gate Array (FPGA) accelerator based on the Convolutional Tsetlin Machine (CTM) is presented. The accelerator performs classification of two pattern classes in 4 × 4 Boolean images with a 2 × 2 convolution window. Specifically, there are two separate TMs, one per class. Each TM comprises 40 propositional logic formulas, denoted as clauses, which are conjunctions of literals. Include/exclude actions from the TAs determine which literals are included in each clause. The accelerator supports full training, including random patch selection during convolution based on parallel reservoir sampling across all clauses. The design is implemented on a Xilinx Zynq XC7Z020 FPGA platform. With an operating clock speed of 40 MHz, the accelerator achieves a classification rate of 4.4 million images per second with an energy per classification of 0.6 J. The mean test accuracy is 99.9% when trained on the 2-dimensional Noisy XOR dataset with 40% noise in the training labels. To achieve this performance, which is on par with the original software implementation, Linear Feedback Shift Register (LFSR) random number generators of minimum 16 bits are required. The solution demonstrates the core principles of a CTM and can be scaled to operate on multi-class systems for larger images.

• Bhattarai, Bimal; Granmo, Ole-Christoffer; Lei, Jiao; Andersen, Per-Arne; Tunheim, Svein Anders & Shafik, Rishad Ahmed [Show all 7 contributors for this article] (2023). Contracting Tsetlin Machine with Absorbing Automata, 2023 International Symposium on the Tsetlin Machine (ISTM). IEEE (Institute of Electrical and Electronics Engineers). ISSN 9798350344776. doi: 10.1109/ISTM58889.2023.10455040. Full text in Research Archive
• Tarasyuk, Olga; Rahman, Tousif; Shafik, Rishad Ahmed; Yakovlev, Alexandre; Gorbenko, Anatoliy & Granmo, Ole-Christoffer [Show all 7 contributors for this article] (2023). Systematic Search for Optimal Hyper-parameters of the Tsetlin Machine on MNIST Dataset, 2023 International Symposium on the Tsetlin Machine (ISTM). IEEE (Institute of Electrical and Electronics Engineers). ISSN 9798350344776. doi: 10.1109/ISTM58889.2023.10454969. Full text in Research Archive
• Tunheim, Svein Anders; Lei, Jiao; Shafik, Rishad Ahmed; Yakovlev, Alexandre & Granmo, Ole-Christoffer (2022). A Convolutional Tsetlin Machine-based Field Programmable Gate Array Accelerator for Image Classification. In Shafik, Rishad (Eds.), 2022 International Symposium on the Tsetlin Machine (ISTM 2022). IEEE (Institute of Electrical and Electronics Engineers). ISSN 9781665471169. p. 21–28. doi: 10.1109/ISTM54910.2022.00013. Full text in Research Archive Show summary

  This paper presents a Field Programmable Gate Array (FPGA) implementation of an image classification accelerator based on the Convolutional Tsetlin Machine (CTM). The work is a concept design, and the solution demonstrates recognition of two classes in 4 × 4 images with a 2 × 2 convolution window. More specifically, there are two sub-Tsetlin Machines (TMs), one per class. A single sub-TM employs 40 clauses, each controlled by 20 Tsetlin Automata. The accelerator features random patch selection, in parallel for all clauses, based on reservoir sampling. The design is implemented in a Xilinx Zync XC7Z020 FPGA. With an operating clock speed of 30 MHz, the accelerator is capable of inferring at the rate of 3.3 million images per second with an additional power consumption of 20 mW from idle mode. The average test accuracy is 96.7% when trained on data with 10% noise. A training session with 100 epochs and 8192 examples takes 1.5 seconds. Due to the limited hardware resources required, the CTM accelerator represents a promising concept for online learning in energy-frugal systems. The solution can be scaled to multi-class systems and larger images.

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